THE ON-CURRENT

In CMOS logic the ON-current is the drain current when V_GS > V_T , i.e., when the source-end of the channel is in strong inversion. The drain current increases with V_DS to reach a maximum value that we have called I_Dsat . Over the years, reduction of the channel length L has been more aggressive than reduction of the supply voltage V_DD , which sets a maximum limit to the bias voltages V_DS and V_GS . This is because not only did a shorter L improve I_Dsat in physically long devices, it also allowed reduction of the area of the device, thereby improving packing density and reducing many of the FET’s capacitances. The last two attributes still apply, but L no longer has such a strong effect on I_Dsat. This is because L is already sufficiently small for the lateral field E_x to attain a high-enough value for velocity saturation to occur over a significant part of the channel. The effect of this is illustrated in, from which it can be seen that the inclusion of velocity saturation (SPICE Level 49 model) gives a much smaller increase in I_Dsat , as L is reduced, than is predicted by the SPICE Level 1 model, which does not limit the electron velocity to v_sat . However, to attain their saturation velocity, the electrons still have to be accelerated over the source-side of the channel, so a high mobility is still desirable. The effect of doubling the mobility in a short-channel N-FET is shown in. Besides the expected increase in I_D in the linear regime, there is some enhancement (about 20%) in I_Dsat . Besides increasing the velocity via μ_eff , the ON-current can also be improved by increasing the channel charge. The SPICE models of Chapter 10 inform us that this means increasing C_ox and/or the putative overdrive voltage (V_GS − V_T ). Ways of increasing C_ox , and the implications for leakage of the channel current to the gate, are discussed in Section 13.1.4. Because CMOS employs only one power supply, V_DD , increasing V_GS would mean increasing V_DS , which, as we have already discussed, is limited by the necessity of keeping E_x << E_y . Additionally, a low value of V_DD is desirable for the many portable electronic products that CMOS has enabled. The alternative option for increasing the overdrive voltage is to reduce the threshold voltage, but this would have serious consequences for the sub-threshold current, as discussed. In circuitry as dense as in CMOS microprocessors, where 10⁸ transistors per square centimetre is common, one cannot afford to have much of a current per FET when the transistor is OFF (V_GS = 0 in an N-FET), otherwise the static power drain would be prohibitive. Unwanted power dissipation also occurs during switching, and is also discussed in.

Date: 2015-01-29; view: 1037