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Transistors for high-speed logic

David L. Pulfrey

Department of Electrical and Computer Engineering

University of British Columbia

Vancouver, BC V6T1Z4


ABSTRACT- Digital logic is a matter of charging and discharging capacitors as quickly as possible. This chapter draws on the material on the DC performance of MOSFETs and HBTs, and on the chapter on capacitance , to explain the features of modern transistors that make them suited to high-speed logic applications. The emphasis is on Si MOSFETs, which, in the form of complementary MOS technology (CMOS),1 have enabled the ULSI-circuitry2 that has brought electronics into the lives of so many people. At lower levels of integration, and in applications where speed is more important than static power dissipation, emitter-coupled logic (ECL) using HBTs is a viable technology; it is considered at the end of this chapter.  


In CMOS, logic gates comprise pairs of n- and p-type enhancement-mode MOSFETs. We have only considered the former so far, but the latter can be easily envisaged by changing all doped regions from n-type to p-type, and by reversing the polarity of the applied voltages. In CMOS technology, the threshold voltage of the P-FET is usually made to be opposite, and nearly equal in magnitude, to that of the N-FET. A complementary pair of transistors is shown at the end of the CMOS processing sequence in. In a sub-circuit of one P-FET and one N-FET, the two gates of the two transistors are connected together, and the threshold voltages are such that in either of the logic states only one of the transistors is ON. Thus there is, in principle, no static power drain. This was the feature that made CMOS an immediate success when it was first introduced in the 1960s. Another attribute is that CMOS logic gates can be made with much fewer transistors than their ECL rival. Further, in integrated circuits, each transistor has to be contacted at the top surface, and it is difficult to imagine a more compact arrangement than that exhibited by CMOS, in which two of the contacts (source and drain) are so closely aligned with the third contact (gate). The CMOS industry is huge, and has its own roadmap to chart a path towards ever smaller devices. Technology nodes have been identified, which roughly refer to the minimum line-width or line-spacing that can be achieved by a given CMOS technology. Technologies at 90 nm, 65 nm, and 45 nm have been progressively introduced between 2003 and 2008. Each node number is approximately -times smaller than the previous one, so, if this shrinking were achieved in the two dimensions of the surface, the size of the object would be halved. This pays homage to Moore’s Law, in which the co-founder of Intel observed in 1965 that the number of transistors per square inch on ICs was doubling every year. Transistor channel lengths can be considerably smaller than the technology-node number because of the lateral diffusion of the source and drain implants under the gate, and because of the halo regions. The process of systematic shrinking is called scaling; it has driven the high-performance end of the digital electronics industry for more than 40 years. In fact, it is the industry’s paradigm: make transistors smaller and circuits denser, then new applications will appear and jobs and profits will grow. It is not just the lateral physical dimensions that are scaled, but also the vertical dimensions, the supply voltage, and the doping density. These changes have to be made in concert in order to preserve the long-channel operation of the transistor, i.e., to ensure that the charge at the source end of the channel Qn (0) is controlled predominantly by the vertical field issuing from the gate. It is becoming increasingly challenging to continue shrinking devices while simultaneously improving device performance, as we shall see in the following sections of this chapter.

Date: 2015-01-29; view: 615

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