Clocked RS flip-flop

We frequently require an RS flip-flop which only reacts to the input state at a specific point in time. This time is determined by an additional clock variable C. Figure 2.7 shows a statically clocked RS flip-flop of this kind. If C = 0, then = = l. In this case the flip-flop stores the old state. For C = 1, we get

R = R' and S = S'.

The flip-flop then behaves like a normal RS flip-flop.

Fig. 2.7 - Statically clocked RS flip-flop.

Clocked D flip-flop

We shall now examine how the value of a logic variable D can be stored using the flip-flop in Fig. 2.7. We have seen that Q = S if complementary input states are applied and C = 1. In order to store the value of a variable D, we therefore need only make S = D and R = . The inverter G₅ in Fig. 2.8 is used for this purpose. In the resulting data latch, Q = D as long as clock C = 1. This may also be seen from the truth table in Fig. 2.9. Due to this property, the clocked data latch is also known as a transparent D flip-flop. If we make C = 0 the existing output state is stored.

Fig. 2.8 - Transparent D flip-flop (D latch). Fig. 2.9 - Truth table for the transparent

D-flip-flop.

Fig.2.10 - Practical implementation of a Fig. 2.11 - Circuit symbol for a transparent transparent D flip-flop. D flip-flop.

We can see that NAND gate G₄ in Fig. 2.8 acts as an inverter for D when C = 1. Inverter G₅ can therefore be omitted, producing the practical implemen­tation of a D latch shown in Fig. 2.10 the circuit symbol is given in Fig. 2.11.

IC types:

74LS75 (TTL); 10133 (ECL); 4042 (CMOS)

Date: 2015-01-12; view: 1160