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Types of transfers supported by interconnection structure.· Memory to CPU: The CPU reads an instruction or unit of data from memory. · CPU to Memory:The CPU writes a unit of data to memory. · I/O to CPU: The CPU reads data from I/O device via an I/O module. · CPU to I/O: The CPU sends data to the I/O device. · I/O to or from the Memory: For these two cases, an I/O module is allowed to exchange data directly with memory, without going through the CPU, using direct memory access (DMA).
Multiplexer is a functional device which permits to two or more channels of data link to use the same common device of data transfer jointly.
Command signals specify operations to be performed. Typical control lines include: q Memory Write: Causes data on the bus to be written into the addressed location. q Memory Read: Causes data from the addressed location to be placed on the bus. q I/O Write: Causes data on the bus to be output to the addressed I/O port. q I/O Read: Causes data from the addressed I/O port to be placed on the bus. q Transfer ACK: Indicates that data have been accepted from or placed on the bus. q Bus Request: Indicates that a module needs to gain control of the bus. q Bus Grant: Indicates that a requesting module has been granted control of the bus. q Interrupt request: Indicates that interrupt is pending. q Interrupt ACK: Acknowledges that the pending interrupt has been recognized. q Clock: Used to synchronize operations. q Reset: Initializes all modules. The operation of any bus is as follows: If one of the modules “wishes” to send data to another, it must do two things: 1. Obtain the use of the bus; 2. Transfer data through the bus. If one of the modules “wishes” to receive data from the other module it must do: 1. Obtain the use of the bus; 2. Send request to the other module, by putting the corresponding code on the address lines after formation signals on the certain control lines.
Computer systems contain a number of different buses that provide pathways between components at various levels of the computer systems hierarchy. Date: 2015-12-24; view: 3864 |