With synchronous timing the occurrence of events on the bus is determined by a clock.
The bus includes a clock line upon which a clock transmits a regular sequence of alternating 1s and 0s of equal duration. A single 1-0 transmission is referred to as a clock cycle (bus cycle) and defines a time slot (číňĺđâŕë).All other devices on the bus can read the clock line, and all events start at the beginning of a clock cycle. Other bus signals may change at the leading edge of the clock signal.
Ø With asynchronous timing the occurrence of one event on a bus follows and depends on the occurrence of a previous event.
Simple to implement and test
Less flexible: all devices are tied to a fixed clock rate
More complex to implement and test
The system can’t take advantage of advances in device performance
Allow to use newer technology; mixture of
slow and fast devices
In actual implementations, electronic switches are used. The output gate of register is capable of being electrically disconnected from the bus or placing a 0 or a 1 on the bus. Because it supports these three possibilities, such a gate is said to have a three—stateoutput. A separate control input is used either to enable the gate output to drive the bus to 0 or to 1 or to put it in a high-impedance (electrically disconnected) state. The latter state corresponds to the open-circuit state of a mechanical switch.
PCI Bus Lines (Optional)
PCI Bus Lines (required)
z Interrupt lines
y Not shared
z Cache support
z 64-bit Bus Extension
y Additional 32 lines
y Time multiplexed
y 2 lines to enable devices to agree to use 64-bit transfer
z JTAG/Boundary Scan
y For testing procedures
1. Systems lines
y Including clock and reset
2. Address & Data
y 32 time lines for address/data
y Interrupt & validate lines
3. Interface Control
§ Control the timing transactions and provide coordination among initiators and targets
y Not shared
y Direct connection to PCI bus arbiter
5. Error lines
Synchronous Bus (SB)
On a SB all devices derive timing information from a common clock line.
Equally spaced pulses on this line define equal time intervals; each interval constitutes a bus cycle, during which one data transfer can take place.
Such a scheme is illustrated below. In the scheme the address and data lines are shown as high and low at the same time (this indicates that some lines are high and some low, depending on the particular address or data pattern being transmitted). The crossing points indicate the times at which these patterns change.
A signal line in an indeterminate state (or high impedance state) is represented by an intermediate level halfway between the low and high signal levels.
The sequence of events during an input (read) operation.
At time t0 the processor places the device address on the address lines and sets the mode control lines to indicate an input operation. This information travels over the bus at a speed determined by its physical and electrical characteristics. The clock pulse width t1 –t0 should be chosen such, that it is greater than maximum propagation delay between the CPU and any devices connected to the bus. It should also be wide enough to allow all devices to decode the address and control signals so that the addressed device can be ready to respond at time t1. The addressed device, recognizing, that an input operation is requested, places its input data on the data lines at time t1. At the end of the clock cycle, that is at time t2, the CPU strobes the data lines and loads the data into its input buffer (here, “strobe” means to determine the value of the data at a given instant). For data to be loaded correctly into a storage device, the data must be available at the input of that device for a period greater than the setup time of the device. Hence, the period t2 –t1 must be greater than the maximum propagation time on the bus plus the setup time of the input buffer register of the CPU.
The procedure for an output operation is similar to that for the input sequence. The processor places the output data on the data lines when it transmits the address and the mode information. At time t1, the addressed device strobes the data lines and loads the data into its data buffer.
The synchronous bus scheme is simple and results in a simple design for the device interface. The clock speed must be chosen such that it accommodates the longest delays on the bus and the slowest interface. Note, that the CPU has no way of determining whether the addressed device has actually responded. It simply assumes that at t2 the output data have been received by I/O device or the input data are available on the data lines; if, because of malfunction, the device does not respond, the error will not be detected.