Parity bit

The simplest method of error detection consists of transmitting a parity bit p. Even or odd parity can be defined. For even parity check, the parity bit added to the data word is set to zero if the number of ones in the data word is even. It is set to one if this number is odd. This means that the total number of ones transmitted in a data word including parity bits is always even, or, for odd parity, always odd.

The even parity bit can also be interpreted as the sum (modulo-2) of the data bits. This checksum can be calculated as the exclusive-OR of the data bits.

The implementation of a parity generator is shown in Fig. 3.14. The exclusive-OR gates can be in any sequence. It is chosen such that the sum of the delay times involved remains as small as possible.

For error detection purposes, the parity bit is stored together with the data bits. When the data are read out, the parity can then be regenerated as shown in Fig. 3.15 and compared with the stored parity bit by an exclusive-OR operation. If they differ, an error has occurred and the error output becomes f = 1. This allows each single-bit error to be detected. However, no correction is possible, since the bit containing the error cannot be located. If several bits contain errors, an odd number of errors can be detected, whereas an even number cannot.

Fig. 3.14 - Parity generator for even parity with 8 inputs.

IC types: 8-bit: SN 74180 (TTL); 9-bit: SN 74 S280 (TTL);

12-bit: MC 10160 (ECL); MC 14531 (CMOS)

Fig. 3.15 - Data memory with parity checking (using 8-bit data words as an example).

Date: 2015-01-12; view: 1296