Shifter NetworksWe consider next how large shifters can be realized using the kbit pshifter modules described. We consider only the case of unidirectional rightshift. In what follows we assume that all shifters and shifter modules are of this unidirectional type, without explicitly saying it each time. The modifications for left and for bidirectional shift are left for Exercise 4.40.
An nbit pshifter can be implemented with n/k kbit pshifter modules as illustrated in Figure 1.57. The p least significant inputs of the (m+1)st module are the same as the p most significant inputs of the mth module. The delay of this shifter is the same as the delay of a shifter module.
Fig. 1.57  Right pshifter network (Sift control not shown).
A 12bit 3shifter, implemented by three 4bit 3shifter modules, is illustrated in n The mode of operation is shift right 0, 1, 2, or 3 places with 0 insert.
Fig. 1.58  A 12bit right 3shifter.
An nbit qshifter can be implemented in several ways using kbit pshifter modules (n > k, q >p). One such implementation is described in the following example.
Figure 1.59 shows the implementation of an 8bit 7shifter using 4bit lshifter modules and a 2input binary decoder. The input is a = (a_{7} , . . . , a_{0}), the output is b = (b_{7}, … , b_{0}), and the operation mode is Rotate Right 0, 1, . . . , 7 position.
The shifter network is organized as a rectangular array of shifter modules. Each row corresponds to an 8bit 1shifter. The first row can rotate 0 or 1 positions, the second row can rotate 2 or 3 positions, and so on, the last row rotating 6 or 7 positions. The decoder enables one of the rows, and the outputs of the rows use a wiredOR connection.
Fig. 1.59  Array implementation of an 8bit 8shifter (right rotate only).
Date: 20150112; view: 712
