Element with the open collector

The problem sometimes arises that a large number of gate outputs must be logically linked. For 20 outputs, for instance, a gate with 20 inputs would be required with 20 individual lines leading to them. This complexity can be avoided by using gates with an open-collector output. As shown in Fig. 1.5, their output stage consists merely of an npn transistor whose emitter is connected to ground. Outputs of this kind can simply be paralleled, unlike the push-pull output stages otherwise used, and provided with a common collector resistor as in Fig. 1.5.

The output potential therefore only goes high if all the outputs are high. Consequently, in positive logic an and operation is produced. On the other hand we can see that the output voltage then goes low if one or more of the outputs assumes the L state. We therefore have an or operation in negative logic. As the

Fig. 1.5 - Logical linking of open-collector gate outputs.

Fig. 1.6 - Representation of a wired-AND operation with logic symbols.

operation is realized by the external wiring, it is referred to as a wired-AND or wired-OR circuit. As the gates are at low impedance in the L state only, they are also known as active-low outputs. The wired-AND operation is represented using logic symbols as shown in Fig. 1.6.

An oil operation can also be implemented using open-collector outputs by applying the wired-AND operation to the complemented variables. De Morgan's law states that:

The corresponding circuit is shown in Fig. 1.7.

Fig. 1.7 - Wired-OR circuit with open-collector outputs.

A disadvantage of using open-collector outputs is that the output voltage rises more slowly than with push-pull outputs, because the circuit capacitances can only charge up via resistor R_c. In this respect, open-collector TTL gates have the same disadvantages as the RTL circuits. There, the logical linking can likewise be interpreted as a wired-AND operation.