Timing considerations

For a satisfactory operation of the memory, a number of timing conditions must be observed. Figure 3.31 shows the sequence of a write operation. To prevent the data being written into the wrong cell, the write command must not be applied until a certain time has elapsed after definition of the address. This time is called the address setup time t_AS . The duration of the write pulse must not be less than the minimum value t_WP (write pulse width). The data are read in at the end of the write pulse. They must be valid, i.e. stable, for a minimum period prior to this. This time is called t_DW (Data Valid to End of Write). In a number of memories the data and addresses must also be present for a further time t_H after the end of the write pulse (Hold Time). As can be seen from Fig. 3.6, the time required to execute a write operation is expressed as

t_W = t_AS + t_WP + t_H

This is referred to as the Write Cycle Time.

Fig. 3.31 - Timing of a write operation.

t_AS = Address Setup Time

t_WP = Write Pulse Width

t_DW = Data Valid to End of Write Time

t_H = Hold Time

Fig. 3.32 - Timing of a read operation.

t_AA = Address Access Time

The read operation is shown in Fig. 3.32. After the address is applied, it is necessary to wait for time t_AA until the data at the output are valid. This time is referred to as the Address Access Time or simply Access Time.

A list of some of the most widely-used static RAMs in bipolar and CMOS technology is given in Fig. 3.33

Fig. 3.33 - Examples of static RAMs.

¹ Containing lithium battery; data retention: 10 years

² Hybrid circuit (module)

Manufacturers: Cy = Cypress, Da = Dallas, Fu = Fujitsu, Hi = Hitachi, Hm = Hybrid Memory, Id = IDT, Is = Inmos, Mh = Matra Harris, Na = National, Ne = NEC, St = SGS-Thomson, To = Toshiba, Vt = VTI

Date: 2015-01-12; view: 1108