Memory unit is called RAM if any location can be accessed for Read or Write operation in some fixed amount of time that is independent of the location?s address

Memory cells are usually organized in the form of an array, in which each cell is capable of storing one bit of information.

For semiconductor memories one of the key design issues is the number of bits of data that may be read/written at a time.

At one extreme is an organization in which the physical arrangement of cells in the array is the same as the logical arrangement (as perceived by the processor) of words in the memory: the array is organized into W words of B bits each and B bits are read/written at a time.

Logically, the memory array is organized as 4 square arrays of 2048 by 2048 elements. The elements of the array are connected by horizontal (row) and vertical (column) lines. Each horizontal line connects to the Select terminal of each cell in its row, and each vertical line connects to the Data-In/Sense terminal of each cell in its column.

Address lines supply address of the word to be selected. In this example 11 address lines are used to select one of 2048 rows; additional 11 address lines select one of 2048 columns. Four data lines are used for input and output of 4 bits to and from a data buffer. The row line selects which row of cells is used for reading or writing. Since only 4 bits are read/written to this DRAM, there must be multiple DRAMs connected to the memory controller in order to read/write a word of data to the bus.

Integrated circuits are mounted on packages of DIP (dual in-line package) type: pins are located in 2 rows(lines). The number of pins is usually less or equal to 32.

Fig. (a) shows an example EPROM package (8-Mbit chip). It is ?one-word-per-chip? package. It includes 32 pins, which support following signal lines:

v (A0 ? A19) the address of the word being accessed;

v (D0 ?D7)the data to be read out, consisting of 8 lines;

v V_cc the power supply;

v V_ss the ground pin;

v CE a chip enable;

v V_pp a program voltage that is supplied during programming.

Fig. (b) shows an example DRAM pin package (16-Mbit chip organized as 4M ^. 4.

Since RAM can be updated, the data pins are input/output.

The write enable (WE) and output enable (OE) pins indicate whether this is write or read operation.

RAS means row address select, and CAS ? column address select.

If RAM chip contains only 1 bit per word, then we will need a number of chips equal to number of bits per word. Fig. Module Organisation (1) shows how a memory module consisting of 256K 8?bit words could be organised. For 256K words an 18-bit address is needed and is supplied to the module from some external source. The address is presented to 8 chips, each of which provides the input/output of 1 bit.

When the larger memory is required, an array of chips is needed. The possible organization of 1Mbyte memory is shown in Fig. Module Organisation (2). In this case, we have 4 columns of chip, each column contains 256K words. 20 address lines are needed. The 18 of them are routed to 32 modules. The other 2 are input to a group select logic module, that sends a chip enable signal to one of 4 columns of modules.

Date: 2016-06-13; view: 10