Problems for Self-Testing on Module II

1. Many instruction sets contain the instruction NOP, meaning no operation, which has no effect on the CPU state other than incrementing the program counter. Suggest some uses of this instruction.

2. Suppose a stack is to be used by the CPU to manage procedure calls and returns. Can the program counter be eliminated by using the top of the stack as a program counter?

3. Convert the following formulas from reverse Polish to infix:

a. AB + ? + D

b. AB/CD/+

c. ABCDE + X X /

d. ABCDE + F/ + G - H/ X +

4. Convert the following formulas from reverse Polish to infix:

a. AB + ? + D

b. AB/CD/+

c. ABCDE + X X /

d. ABCDE + F/ + G - H/ X +

5. Convert the expression A + ? ? ? to postfix notation using Dijkstra's algorithm. Show the steps involved. Is the result equivalent to (A + B) ? ? or A + (B - C)? Does it matter?

6. How many times does the CPU need to refer to memory when it fetches and executes an indirect-address-mode instruction in the instruction is (a)a computation requiring a single operand; (b) a branch?

7. Is there any possible justification for an instruction with two opcodes?

8. Given the following memory values and a one-address machine with an accumulator, what values do the following instructions load into the accumulator?

? Word 20 contains 40.

? Word 30 contains 50.

? Word 40 contains 60.

? Word 50 contains 70.

? Word 60 contains 80.

a. LOAD IMMEDIATE 20

b. LOAD IMMEDIATE 20

c. LOAD IMMEDIATE 20

d. LOAD IMMEDIATE 30

e. LOAD IMMEDIATE 30

f. LOAD IMMEDIATE 30

9. a. If the last operation performed on a computer with an 8-bit word was an addition in which the two operands were 2 and 3, what would be the value of the following flags?

? Carry

? Zero

? Overflow

? Sign

? Even parity

? Half-carry

b. What if the operands were -1 (two?s complement) and +1?

10. When out-of-order complementation is used in a superscalar processor, resumption of execution after interrupt processing is complicated, because the exceptional condition may have been detected as an instruction that produced its result out of order. The program cannot be restarted at the instruction following the exceptional instruction, because subsequent instructions have already completed, and doing so would cause these instructions to be executed twice. Suggest a mechanism or mechanisms for dealing with this situation.

11. If the time slot of the computer is equal to 2 ns and it can perform 2 operations in each slot, what is the throughput of such a computer?

12. A conveyer consists of 5 stages. The times of operations of the stages are 1, 1, 2, 1, and 3 time slots accordingly. What is the maximal frequency of the results outputs if the data samples are input uninterruptedly?

13. Is the answer in the previous problem dependent on the order of the stages?

14. A computer contains 9 parallel-working devices; each of them can perform an operation during 9 time slots. What is the minimal time necessary for such computer to process 9 independent operations?

15. A conveyer consists of k stages, processing during n₁, n₂, n_k time slots accordingly. What is the minimal slots number necessary for such a conveyer to perform m operations?

Module III. Parallelism and Scalability

Super Scalar Processors

Date: 2016-06-12; view: 238