Features of Organization Structure of the Pentium Processors

Procedure of Interruption the Pentium Processors.The Pentium uses two lines request of interruption, namely NMI (Non-Maskable Interrupt) for nonmaskable interruptions and INTR for maskable interruptions named users? interruptions as well. The requests of interruptions via line NMI are always accepted by the processor. The requests via line INTR are accepted only in the case they have the higher level of priority than the currently executed program. Requests INTR may be enabled or disabled by setting the bit of interrupt enable in the interrupt status register. In addition to external interruptions there are many exceptions connected with events which occur during the program execution. Such events are illegal codes of operation, dividing errors, overflowing, etc.

Any of the pointed events forces the processor to transfer the control to the Interrupt Handling Routine. The vector number is appointed to each interrupt or exception. In the case of interrupt via line INTR, the vector number directed by I/O device to the processor after acknowledgment the fact of the interruption. For the rest exceptions the vector number is appointed beforehand. Knowing the vector number the processor defines the initial address of the Interrupt Handling Routine using the Interrupt Descriptor Table. The Pentium processor works together with the Advanced Programmable Interrupt Controller (APIC). Different I/O devices are connected with the processor via APIC which defines their priorities and directs their vector numbers to the processor.

The Pentium processor status register is called EFLAGS, 7 bits of which are shown in Fig. 4.13. Among them are Interrupt enable Flag (IF), Trap Flag (TF), and I/O Privilege Level (IOPL) as well. When IF = 1, interrupts via line INTR are enabled. TF enables trap interrupts after each program instruction. The Pentium processor has rather a complex structure of priorities, in accordance to which routines of the operating system conditionally divided onto 4 groups and each of them is appointed one of the four priority levels. For each of such levels is assigned its address space of the processor. When switching from one to another privilege level many tests are executed realizing so-called mechanism of lockout. Such architecture allows designing operating systems with high degree of security. But the Pentium processor may work in the very simple mode as well, when there is no privilege and all the programs function in the same memory segment. Let us consider such simple mode. At occurring exception and after receiving an interrupt request, the processor executes operations listed below.

1. Pushes the number of Current Segment (CS) and the instruction pointer EIP to the processor stack pointed by the ESP register.

2. If the exception is initiated by a nonstandard situation while the program execution, pushes the code of the exception to the stack.

3. If necessary, clears IF to disable further requests of the same source.

4. Using the interrupt vector number, finds the initial address of the Interrupt Handling Routine in the Interrupt Descriptor Table and pushes it into EIP and after this continues the instructions execution.

Having serviced the request (e.g., transferred input or output data), the Interrupt Handling Routine returns the control to the interrupted program by executing instruction IRET, which restore values of registers EIP, CS, and processor status from the stack.

To enable interrupts in the processor, execute instruction STI setting flag IF of the processor status register to 1.

External Interrupt Considerations.The Pentium processor recognizes the following external interrupts: BUSCHK#, R/S#, FLUSH#, SMI#, INTT, NMI, and INTR. These interrupts are recognized at instruction boundaries. On the Pentium processor, the instruction boundary is the first clock in the execution stage of the instruction pipeline. This means that before an instruction is executed, the Pentium processor checks to see if any interrupts are pending. If an interrupt is pending, the processor flushes the instruction pipeline and then services the interrupt. The priority order of external interrupts is as shown below: BUSCHK#, R/S#, FLUSH#, SMI#, INTT, NMI, INTR.

Model Specific Registers. The Pentium processor defines certain Model Specific Registers that are used in execution tracing, performance monitoring, testing, and machine check errors. They are unique to the Pentium processor and may not be implemented in the same way in future processors.

Two new instructions, RDMSR and WRMSR (read/write model specific registers), are used to access these registers. When these instructions are executed, the value in ECX specifies which model specific register is being accessed. Table 4.1 lists all-model specific registers and the corresponding values (in Hex) that need to be loaded into ECX to access them.

Table 4.1.

Date: 2016-06-12; view: 178