Function and Construction of Computer Memory

How the Hardware Devices Interact with Each Other. Fig. 1.1 illustrates how the primary hardware components interact. Data can be placed in memory by input devices and auxiliary storage devices (you can read data into memory from a disk or you can type the data at the keyboard). Once the data is in main memory, the processor can manipulate that data into information. The processor will retrieve data from memory and it may also temporarily store calculations and other operations in memory while it is displayed using an output device or it can be saved to an auxiliary storage device. In some computers, the smallest addressable unit of information is a memory word. Successive memory addresses refer to successive memory words, and the machine is called word-addressable. Alternatively, individual memory bytes may be assigned distinct addresses, thus yielding a byte-addressable computer. In such a case, a memory word contains one or more memory bytes, which can be addressed individually. For example, in a byte-addressable 32-bit computer, each memory word contains 4 bytes. A possible way of address assignment in this case is shown in Fig. 1.20. The address of a word is that of its high-order byte. Thus word addresses are always integer multiples of 4. The use of memory hierarchical structure is the traditional decision of data storage problem (Fig. 1.21) [13], [27], [53], [55], [59], [60], [61], [62].

The RAM is usually designed to store and retrieve data in word-length quantities. In fact, the number of bits actually stored or retrieved in one RAM access is the most usual way of defining the word length of a computer. Consider, for example, a byte-addressable computer with the addressing structure of Fig. 1.20, whose instructions generate 24-bit addresses. When a 24-bit address is sent from the CPU to the RAM unit, the high-order 22 bits determine which word will be accessed. If a byte quantity is specified, the low-order 2 bits of the address specify which byte location is involved. In the case of a Read operation, other bytes may be fetched from the RAM, but the CPU ignores them. However, if the byte operation is a Write, the control circuitry of the RAM must ensure that the contents of other bytes of the same word are not changed. From the system standpoint, we can view the RAM unit as a "black box." Data transfer between the RAM and the CPU takes place through the use of the two CPU registers MAR (memory address register) and MDR (memory data register). Let MAR be k bits long and MDR n bits long. Thus the RAM unit may contain up to 2^k addressable locations. During a "memory cycle," n bits of data are transferred between the RAM and the CPU. This transfer takes place over the memory bus, which consists of k address lines and n data lines. It also includes the control lines Read, Write, and Memory Function Completed (MFC) for coordinating data transfers. In the case of byte-addressable computers, another control line may be added to indicate when only a byte, rather than a full word of n bits, is to be transferred. The connection between the CPU and the RAM is shown schematically in Fig. 1.22. The CPU initiates a memory operation by loading the appropriate data into registers MDR and MAR, then setting either the Read or Write memory control line to 1. When the required operation is completed, the memory control circuitry indicates this to the CPU by setting MFC to 1.

A useful measure of the speed of memory units is the time that elapses between the initiation of an operation and the completion of that operation (for example, the time between Read and MFC). This is referred to as the memory access time. Another important measure is the memory cycle time. This is the minimum time delay required between the initiations of two independent memory operations (for example, two successive Read operations). The cycle time is usually slightly longer than the access time. The difference is highly dependent upon the implementation details of a particular RAM unit.

Recall that a memory unit is called a random-access memory (RAM) if any location can be accessed for a Read or Write operation in some fixed amount of time that is independent of its position or address. Main memory units are of this type. This distinguishes them from serial, or partly serial, access storage devices such as magnetic tapes and disks. Access times on the latter devices depend upon the address or position of the data.

The basic technology for the implementation of main memories uses semiconductor integrated circuits. The speed problem arises because the CPU can usually process instructions and data faster than they can be fetched from compatibly priced conventional RAM units. That is, the RAM cycle time is the bottleneck in the system. In many cases, high-speed performance is required. This may be achieved in a number of ways. One possibility is the use of a cache memory - a small and fast memory that is inserted between the larger and slower RAM and the CPU. It serves to hold the currently active segments of a program and its data. Another technique is to divide the system into a number of memory modules. Addressing is arranged so that successive words in the address space are in different modules. If requests for memory access tend to involve consecutive addresses, such as in executing straight-line program segments, then the accesses will be to different modules. Since parallel access to these modules is possible, the average rate of fetching words from the RAM to the CPU can be increased. The technique is called memory interleaving.

Before discussing the problem of RAM size, let us introduce the notion of virtual memory, which is an important concept related to memory organization. So far, it has been assumed that the addresses generated by the CPU directly specify physical locations in the RAM. This may not always be the case. For reasons that will become apparent later, data may be stored in physical memory locations that have addresses different from those specified by the program. The memory control circuitry translates the address specified by the program into an address that can be used for accessing the physical memory. In such a case, an address generated by the CPU is referred to as a virtual address. The virtual address space, which is used by the program, is mapped onto the physical memory where data is actually stored. The mapping function is implemented by memory control circuitry often called the memory management unit. This mapping function may be changed dynamically during program execution according to system requirements.

The concept of virtual memory can be used to deal with the problem of size of the RAM. Almost every computer reaches a point in its existence where programmers require more memory than is available. It is often more economical to use magnetic disks to increase the available memory space before the maximum possible size (2^k in the above discussion) of RAM is reached. The programmer would like to address data stored on the bulk storage devices as if it were in the RAM. It is at this point that the concept of virtual memory can be utilized. Data is addressed in a virtual address space that can be as large as the addressing capability of the CPU. At any given time, only the active portion of this space is mapped onto the physical RAM. The remaining virtual addresses are mapped onto the bulk storage devices used. As the active portion of the virtual address space changes during program execution, the memory management unit changes the mapping function and transfers data between the bulk storage and the RAM as required.

Thus, during every memory cycle, an address-processing mechanism (hardware and/or software) determines whether or not the address generated by the CPU is in the physical RAM unit. If it is, then the proper word is accessed and execution proceeds. If it is not, a contiguous block of words containing the desired word is transferred from the bulk storage to the RAM, displacing some block in the RAM that is currently inactive. Because of the time required for movement of blocks between the bulk storage and the RAM, there is speed degradation in this type of a system. However, by a suitable choice of block replacement methods, it is possible to have reasonably long periods during which the probability is high that the words accessed by the CPU are in the physical RAM unit. It should be noted that block movement could be achieved by DMA cycle-stealing techniques. Therefore, other active programs that are resident in the RAM can be executed while a block transfer is taking place for a particular program.

Internal Organization of Memory Chips.A memory cell is capable of storing 1 bit of information. A number of cells are usually organized in the form of an array. One such organization is shown in Fig. 1.23. Each row of cells constitutes a memory word, and all cells of a row are connected to a common line referred to as the word line. The word lines are driven by the address decoder on the chip. The cells in each column are connected by two lines, known as bit lines, to a Sense/Write circuit. The Sense/Write circuits are, in turn, connected to the data input-output lines of the chip. During a Read operation, the Sense/Write circuits sense, or read, the information stored in the cells selected by a word line and transmit this information to the output data lines. During a Write operation, they receive input information and store it in the cells of the selected word.

Fig. 1.23 shows a memory chip consisting of 16 words of 8 bits each, usually referred to as a 16 × 8 organization. The data input and the data output of each Sense/Write circuit are connected to a single bidirectional data line in order to reduce the number of pins required. In addition to address and data lines, two control lines, R/ and CS, are provided. The R/ (Read/ ) input is used to specify the required operation. The CS (Chip Select) input is needed to select a given chip in a multichip memory system.

Dynamic memories (DRAM). The basic idea of the dynamic memory is very simple. Information is stored in the form of a charge on a capacitor. If the capacitor discharges very slowly, the stored information will be retained for some time. Such memories are capable of storing information only for period of time of the order of a few milliseconds. If it is required to store the information for a longer time, restoring the capacitor charge to its full value must periodically refresh the contents of each memory cell.

An example of a dynamic memory cell is shown in Fig. 1.24. It consists of a capacitor C and a transistor T. In order to store information in this cell, transistor T is turned On and an appropriate voltage V is applied to the bit line. This causes a known amount of charge to be stored on the capacitor. After the transistor is turned Off, the capacitor discharges slowly. This is due to the capacitor's own leakage resistance and the fact that the transistor conducts a small amount of current, of the order of picoamperes, even when it is turned Off. Hence, the information stored in the cell can be retrieved correctly only if it is read before the charge on the capacitor drops below some threshold value. During a Read operation, the bit line is placed in a high-impedance state, and the transistor is turned On. A sense circuit connected to the bit line is used to determine whether the charge on the capacitor is above or below the threshold value. Because this charge is small, the read operation is quite involved. The details are beyond the scope of this text. However, we should note one important feature. During the process of reading the contents of the cell, the charge on the capacitor is restored to its original value. That is, a memory cell is refreshed every time its contents are read.

A typical organization of a 64K × 1 dynamic memory chip is shown in Fig. 1.25. The cells are organized in the form of a square array, where the high- and low-order 8 bits of the 16-bit address constitute the row and column addresses of a given cell, respectively. In order to reduce the number of pins needed for external connections, the row and column addresses are multiplexed on eight pins. During a Read or a Write operation, the row address is applied first. In response to a signal pulse on the Row Address Strobe (RAS) input of the chip, this part of the address is loaded into the row address latch, and a Read operation is initiated on the corresponding row. All cells on this line are read and refreshed. Shortly after the row address is latched, the column address is applied to the address pins. It is loaded into the column address latch under control of the Column Address Strobe (CAS) signal. The information in this latch is decoded and the appropriate Sense/Write circuit is selected. If the R/ control signal indicates a Read operation, the output of the selected circuit is transferred to the data output, DO. For a Write operation, the information at the data input DI is transferred to the selected circuit. This information is then used to overwrite the contents of the cell in the corresponding column.

It is important to emphasize that the application of a row address causes all cells on the corresponding row to be read and refreshed. This takes place during both Read and Write operations. In order to ensure that the contents of a dynamic memory are maintained, each row of cells must be addressed periodically, typical once every 2 ms. This function is usually performed automatically by a Refresh circuit. Some dynamic memory chips incorporate a Refresh facility within the chip itself. In this case, the dynamic nature of the memory is almost completely transparent to the user. Such memory chips are often referred to as pseudostatic. A useful feature that is available on many dynamic memory chips should be mentioned at this point. Consider an application in which a number of memory locations at successive addresses are to be accessed. Assume further that the cells involved are all on the same row inside a memory chip. Since row and column addresses are loaded separately into their respective latches, it is only necessary to load the row address once. Then different column addresses can be loaded during successive memory cycles. The rate at which such block transfers can be carried out is typically doubles that for random access.

Memory System Considerations.The choice of a RAM chip for a given application depends on several factors. Foremost among these are the speed, power dissipation, and size of the chip. In certain situations, other features, such as the availability of block transfers, may be important.

We will now discuss the design of memory subsystems using static and dynamic chips. Consider first a small memory consisting of 64K (65,536) words of 16 bits each. An example of the organization of this memory using 16K × 1 static memory chips is given in Fig. 1.26. A set of four chips is required to implement each bit position. The set corresponds to one column in the figure. Sixteen such sets provide the required 64K × 16 memory. Each chip has a control input called Chip Select. A chip can be enabled to accept data input or to place data on the output bus by setting its Chip Select input to 1. The data output for each chip is of the three-state type. Only the selected chip places data on the output line, while all other outputs are in the high-impedance state. The address bus for this 64K memory is 16 bits wide. The high-order 2 bits of the address are decoded to obtain the four Chip Select control signals. The remaining 14 address bits are connected to all the chips. They are used to access a specific bit location inside each chip of the selected row. The R/ inputs of all chips are also tied together to provide a common Read/ control (not shown).

Next let us consider a large, dynamic memory. The organization of such a memory is essentially the same as that in Fig. 1.26. However, the control circuitry differs in three respects. First, the row and column parts of the address for each chip usually have to be multiplexed. Secondly, a Refresh circuit is needed. Finally, the timing of various steps of a memory cycle must be carefully controlled.

An example of a dynamic memory unit is given in Fig. 1.27. The figure depicts an array of 64 dynamic memory chips and the required control circuitry. The memory chips are assumed to be arranged in a 4 × 16 array, in exactly the same way as in Fig. 1.26. Thus, if individual chips have a 64K × 1 organization, the array has a total storage capacity of 256K words of 16 bits each. The control circuitry provides the multiplexed address and Chip Select inputs, as well as the Row and Column Address Strobe signals (RAS and CAS) to the memory chip array. It is also responsible for generating Refresh cycles as needed. The memory unit is assumed to be connected to an asynchronous memory bus which has 18 address lines, ADRS_17-0; 16 data lines, DATA_15-0; two handshake signals, Memory Request and Memory Function Completed (MFC); and a Read/ line to indicate the type of memory cycle requested.

In order to understand the operation of the control circuitry, let us start by examining a normal memory read cycle. The cycle begins by the CPU asserting the address, the Read/ and the Memory Request lines. The access control block recognizes such a request when the Memory Request signal becomes active, and as a result, the Start signal is set to 1. The timing control block responds immediately by activeting the Busy signal, in order to prevent new requests from being accepted by the access control block, until the cycle ends. Then it loads the row and column addresses into the memory chips by activating the RAS and CAS lines, respectively. During this time, it uses the Row/ line to select first the row address, ADRS_15-8, followed by the column address, ADRS_7-0. The decoder block decodes the 2 most significant bits of the address, ADRS_17,16, and activates one of the Chip Select lines, CS_0-3.

Having obtained the row and column parts of the address, the selected memory chips place the contents of the requested bit cells on their data outputs. This information is transferred to the data lines of the memory bus via appropriate drivers. The timing control block allows for delays in the circuitry involved; then it activates the MFC line, indicating that the requested data is now available on the memory bus. At the end of the memory cycle, the timing block deactivates the Busy signal. The access unit is now free to accept new requests. We should note that the exact time at which various signals are activated and deactivated must be carefully controlled in accordance with the specifications of the particular type of memory chips used.

Consider now a Refresh operation. Refresh requests are generated periodically by the Refresh control block. In response, the access control block starts a memory cycle in the normal way. It indicates to the Refresh control block that it may proceed with a Refresh operation by activating the Refresh Grant line. Note that the function of the access control block is to arbitrate between Memory Access requests and Refresh requests. In the case of simultaneous arrives, Refresh requests are given priority. This is necessary in order to ensure that no stored information is lost.

As soon as the Refresh control block receives the Refresh Grant signal, it activates the Refresh line. This causes the address multiplexer to select the output of the Refresh counter. Hence, the contents of the counter will be loaded into the row address latches of all memory chips when the RAS signal is activated. During this time, the state of the R/ line of the memory bus may indicate a Write operation. It is important to ensure that this does not inadvertently result in new information being loaded into some of the cells being refreshed. The needed protection can be provided in several ways. A possible approach is that, while the Refresh line is active, the decoder block deactivates all CS lines. This prevents any memory chip from responding to the R/ line. The remainder of the Refresh cycle is the same as in a normal cycle. At the end, the Refresh control block increments the Refresh counter in preparation for the next Refresh cycle.

We should note that the Refresh counter is only 7 bits wide, although an 8-bit row address needed. This choice is related to the way in which cells are organized inside the memory chip. The 256 × 256 array in Fig. 1.25 in fact consists of two 128 × 256 arrays, each having its own set of Sense/Write circuits. One row in each of the two arrays is accessed during any memory cycle, depending upon the low-order 7 bits of the row address. The most significant bit of the row address is used only in a normal Read/Write cycle. It selects one of two groups of 256 columns. Because of this organization, the frequency of Refresh operations can be reduced to one-half of what would be needed had the memory cells been organized in a single 256 × 256 array.

The main purpose of the Refresh circuit is to maintain the integrity of the stored information. Ideally, its existence should be transparent to the remainder of the computer system. That is, other parts of the system, such as the CPU, should not be affected by the operation of the Refresh circuit. However, the CPU and the Refresh circuit, in effect, compete for access to the memory. In order to ensure that no information is lost, the Refresh circuit must be given priority. Thus, the response of the memory to a request from the CPU, or from a DMA device, may have to be delayed if a Refresh operation is in progress. The amount of delay caused by Refresh cycles depends upon the mode of operation of the Refresh circuit. During a Refresh operation, all memory rows may be refreshed in succession, before the memory is returned to normal use. A more common scheme is to interleave Refresh operations on successive rows with accesses from the memory bus. This results in Refresh periods that are shorter in duration but more frequent. In either case, the total number of memory cycles lost to refresh operations is typically in the range 3 to 5 percent. Thus the time penalty caused by the need for refreshing is small.

In the case of a synchronous bus, it may be possible to hide a Refresh cycle within the early part of a bus cycle. This can be done if sufficient time remains after a Refresh cycle to carry out a Read or a Write access. Alternatively, the Refresh circuit may request bus cycles in the same manner as any device having a DMA capability. In this case, it may be desirable to use non-interleaved refresh to avoid the overhead that may result from frequent DMA requests.

Date: 2016-06-12; view: 317