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Framing Error CountA framing error is declared if an NSP message is incorrectly encapsulated on the communications link. For ASYNC and RS485 links, this would be any time a FESC character is seen that is not immediately followed by TFESC or TFEND. CAN framing errors are TBD. Runt Packet Count A runt packet is a NSP message that is less than 5 bytes long. Such a fragment cannot be a properly formed NSP message since it cannot contain a source and destination address, control field, and CRC. Runts are counted only if the first byte is equal to the star tracker’s address, which would normally indicate that the packet is addressed to this unit. A zero-length NSP message is not considered a runt. For example, on an ASYNC or RS485 link two FEND characters back-to-back is a valid bus condition and not a runt. Oversize Packet Count An oversize packet is one that has too many bytes in the data field. Packets that are too long cannot fit into the allocated message buffers and so they must be rejected. See section 5.2 for the length constraints. Bad CRC Count This count is incremented every time a properly formatted (in length and framing) NSP message is received where the CRC field does not match with the computed CRC, and where the first byte is equal to the NSP address of the star tracker. FIFO Overflow Count The bootloader does not use FIFO buffers, and will never increment this counter. The application program uses a mix of hardware and software FIFO buffers on its serial inputs. If a FIFO overflows and loses data then this counter will increment. Due to the constraints of the hardware it is not guaranteed that all overflow events will be noticed.
EDAC Memory The supervisor processor supports 512 bytes of EDAC protected memory. These are implemented using software-based triple-redundant storage into conventional SRAM cells. EDAC memory can be read with READ EDAC and READ FILE commands, and written with WRITE EDAC and WRITE FILE commands. The STORE command will save EDAC memory into non-volatile flash memory. Table 33: Supervisor EDAC Memory Map
Asynchronous telemetry is continually recorded using the ADC in the supervisor processor. Synchronous telemetry is recorded in a single snapshot at a time after the functional processor startup as defined by the Sample point value. The result structure and the control structure lengths are maintained in EDAC memory. If the GO command so-specifies, the control structure will be loaded into the functional processor. The functional processor may return a result structure, and the length of that structure will be recorded. The return of the result structure is not atomic, so the result structure length field will slowly grow as individual result packets are received by the supervisor processor. The timeout period determines how long the functional processor should be allowed to run before it is turned off. This is ignored if the GO command stated that the functional processor should be allowed to run indefinitely. The sample point determines when the synchronous telemetry snapshot should be taken. It is measured in seconds after the moment that the /Reset signal on the functional processor is de-asserted. Note that if the sample point value is too long (i.e. longer than the timeout period) the synchronous telemetry may not be sampled. The sequence state shows the power state of the functional processor. Table 34: Sequence States
The functional processor can send notification messages to be stored in the EDAC memory. Only one message can be stored at a time, and a newer message replaces an older one. The length of the currently stored message is stored in EDAC, followed by the message itself. Upon bootup the functional processor will send its ASIC ID sequence, which is a 58 byte structure identifying the chip. At certain points in its program it may send debugging notifications. These are human-readable ASCII strings. They are not NULL terminated, since the message length is stored separately. If the functional processor encounters a serious error it will send an emergency terminate message. This message will be stored in EDAC, and receipt of it will also cause the supervisor to immediately power down the functional processor. Emergency terminate messages are human-readable ASCII. The upper bits of the realtime clock are stored in the EDAC memory. While they are accessible through this route, the dedicated TIME command is recommended instead. Inconsistent data may be obtained if an attempt is made to read the time via the EDAC functions at the same moment as the clock ticks. The STORE command will save a copy of the EDAC memory to non-volatile flash memory, or erase the flash memory page. Upon entry to idle mode (by INIT command) the application program will check the CRC of the flash memory page. If it is correct then it will load the page into EDAC memory. The EDAC Load Source parameter will be set to 1 to indicate this. The first two bytes of EDAC memory will contain the CRC read from flash. If the CRC validation fails it will load default values. The EDAC Load Source parameter will be cleared to 0 to indicate this. The first two bytes of EDAC memory will also be cleared. Erasing the flash page will force the CRC check to fail, causing default values to be loaded. Result Structure Received result data from the functional processor is stored in the result structure. It can be read using the READ RESULT command. Before reading it is a good idea to read the result structure length from EDAC memory. READ RESULT will return NACK if an attempt is made to read beyond the valid areas of the result structure. The format of the result depends on whether the star tracker is being used operationally, or in self-test. In both cases, the structure is made up of sub-structures Operational Result Table 35: Operational Result Structure
The entire operational result structure is 0x0A38 bytes long. Self-Test Result Table 36: Self-Test Result Structure
The complete self-test structure is 0x02CC bytes long. It is possible that the self-test will fail somewhere along the sequence. For example, if the detector is not working the sequence may stall waiting for an image. In this case the structure will be shorter, and the location of the stall may be determined by the missing data. The Combination command will not deal gracefully with a test failure. Return Code The return code is a bitfield that allows the success of the operation to be determined at a glance. New in this revision is a revised set of return codes that clarify interpretation of the sensor status for the end user. The original codes are still set, but are labeled ‘Legacy’ codes. Table 37: Return Code
Master Return The Master Return bit is an overall indicator of the sensor’s confidence in its result. Generally, when this bit is set, the sensor is confident in its return. If this bit is not set, the quaternion and omega fields in the primary telemetry will be zeroed and should not be used.
Date: 2015-12-17; view: 615
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