Direct Memory Access (DMA).

DMA permits to the I/O module and main memory exchange data directly without CPU involvement.

DMA involves an additional module on the system bus (DMA controller). The DMA controller is capable of ?mimicking? (???????) the CPU, indeed, of taking over control of the system from the CPU. The technique works as follows: when CPU wishes to read or write a block of data, it issues a command to the DMA, by sending the following information:

? Whether a read or write is requested.

? The address of the I/O device involved.

? The starting location in memory to read from or write to.

? The number of words to be read or written.

The CPU then continues with other work. It has delegated this I/O operation to the DMA module, and that module will take care of it. The DMA transfers the entire block of data, one word at a time, directly to or from the memory, without going through the CPU, When the transfer is complete, the DMA sends an interrupt signal to the CPU. Thus the CPU is involved only at the beginning and the end of the transfer.

		This approach is nice and simple, as interrupts are handled in strict sequential order. The drawback of this approach is that it doesn?t take into account relative priority or time critical needs.

		This approach is to define priorities for interrupts and to allow an interrupt of higher priority (?estate?) to cause a lower-priority interrupt handler to be itself interrupted. Example. Consider a system with 3 I/O devices: ? a printer (priority 2); ? a disk (priority 4); ? a communication line (priority 5) Let user program begins at t = 0. At t = 10, a printer interrupt occurs, user information is placed on the stack, and execution continues at the printer interrupt service routine (ISR). While this routine is still executing, at t = 15, a communication interrupt occurs. Since communication line has higher priority, the interrupt is honored, the printer ISR is interrupted.
		Multiple Interrupts - Nested

Date: 2016-06-13; view: 72