Memory Barrier Semantics

A memory barrier is a processor instruction that preserves the ordering of read and/or write operations from the perspective of any other processor. Memory barriers include processor instructions with acquire, release, and fence semantics. These semantics describe the order in which results of an operation become visible.

· Acquire semantics mean that the results of the operation are visible before the results of any operation that appears after it in code.

· Release semantics mean that the results of the operation are visible after the results of any operation that appears before it in code.

· Fence semantics combine acquire and release semantics. The results of an operation with fence semantics are visible before those of any operation that appears after it in code and after those of any operation that appears before it.

Figures 3, 4, and 5 show how acquire, release, and fence semantics affect the order in which the results of operations are visible.

In Figure 3, Operation 3 has acquire semantics. This means that the results of Operation 3 are visible before the results of Operations 4, 5, and any other operation that follows it in code. The acquire semantics do not, however, affect the order in which the results of Operations 1 and 2 are visible. These results might appear before or after those of Operations 3, 4, or 5.

Figure 3. Acquire Semantics

In the next figure (Figure 4), Operation 3 has release semantics. Therefore, the results of Operations 1 and 2, which precede it, are visible before the results of Operation 3 are visible. However, the order in which the results of Operation 3 are visible with respect to Operations 4 and 5 is not specified. The results of these operations, which follow the release instruction, might be visible before or after those of Operation 3.

Figure 4. Release Semantics

Finally, in Figure 5, Operation 3 has fence semantics. This means that the results of Operations 1 and 2 are visible before the result of Operation 3, and that the result of Operation 3 is visible before the results of Operations 4 and 5.

Figure 5. Fence Semantics

On x86 and x64-based hardware (including AMD64 and the Intel Extended Memory 64 Technology), the InterlockedXxx and ExInterlockedXxx functions have both acquire and release semantics by default. The Intel Itanium architecture, however, can execute operations that have either acquire or release semantics (and not both) faster than those that have both. On Windows Vista, Microsoft plans to provide versions of the InterlockedXxx and ExInterlockedXxx functions that support either acquire or release semantics.

In addition, Microsoft CL 14.0.0 and later versions tighten the restrictions on the types of reordering that can occur around volatile variables. In these compilers, reads from volatile locations are treated as acquires and writes to volatile locations are treated as releases on hardware architectures that support these semantics.

Date: 2015-12-24; view: 819